FIG. 32 is a cross-sectional drawing showing the structure of a conventional thin film transistor 900 (referred to hereinafter as a TFT). The TFT 900 is an n-channel type TFT. As shown in FIG. 32, a gate electrode 920 is formed on an insulating substrate 911, which is a glass substrate or the like, for example. A gate insulation film 930 is formed so as to cover the insulating substrate 911 including the gate electrode 920. A channel layer 960 formed of microcrystalline silicon is formed on the upper face of the gate insulation film 930 so as to overlap the gate electrode 920 as viewed from above. At respective lateral end parts of the channel layer 960, silicon layers 940a and 940b made of silicon doped with a high concentration of n-type impurity (referred to hereinafter as the “n+ silicon layer”) are formed. The n+ silicon layer 940a functions as the source region, and the n+ silicon layer 940b functions as the drain region. A source electrode 950a electrically connected to the upper face of the n+ silicon layer 940a extends in the leftward direction, and a drain electrode 950b electrically connected to the upper face of the n+ silicon layer 940b extends in the rightward direction. Furthermore, a protective film 970 is formed so as to cover the insulating substrate 911 including the source electrode 950a, the drain electrode 950b, and the channel layer 960.
Since the microcrystalline silicon is crystalline silicon, its electrical conductivity is higher than that of amorphous silicon. Therefore, for the TFT 900 equipped with a channel layer 960 formed of microcrystalline silicon, the ON current becomes high in comparison to a TFT having the same structure as the channel layer 960 formed of amorphous silicon.
Japanese Patent Application Laid-Open Publication No. S62-30375 discloses a back gate type TFT equipped with a gate electrode arranged upon an insulating substrate, a channel layer arranged above the gate electrode, and within the same plane as the channel layer, a source electrode and drain electrode arranged so as to sandwich the channel layer. Since the channel layer is directly connected to the source electrode, and since the channel layer is directly connected to the drain electrode, resistance between the source electrode and the drain electrode becomes small, and the operating speed of the TFT of this structure improves.
Japanese Patent Application Laid-Open Publication No. H8-8440 discloses a back gate type TFT provided with a channel layer composed of intrinsic amorphous silicon. A p-type layer doped by a p-type impurity is formed, among the surfaces of the channel layer of this TFT, at the surface opposite to the gate electrode (referred to hereinafter as the “back channel side”). The p-type layer prevents positive ions from the exterior from attaching to the back channel side surface of the channel layer and prevents electrical charging of the protective film, and therefore, thereby reducing leak current flowing to the back channel side of the channel layer.